Multi- and Many- core support evolved over the years in ERIKA Enterprise, starting with a first implementation done in year 2000 with ERIKA Enterprise v2.x, and recently with a complete re-implementation performed with ERIKA v3.x. The following paragraphs provide a short description of the two supports.
Multi-core support in ERIKA Enterprise V2.x
ERIKA Enterprise and RT-Druid have explicit support for multicore architecture. Multiprocessor systems are being considered as an economically viable alternative to support this increasing computational demand. However, the usage of multiprocessor hardware in small embedded system poses problems to developers ranging from concurrency to load distribution.
The ERIKA Enterprise project started in year 2000 with the idea of supporting new multicore chips. The first chip were ERIKA was working was, in year 2001, the ST "Janus" chip, featuring two ARM7 cores on a single chip, and a crossbar switch to connect the two cores with two separate memory banks. The memory map on that chip was swapped, thus requiring an Asymmetric Multi Processor (AMP) approach, where a separate copy of the RTOS is needed for each core.
That initial implementation was the starting point from which all other implementation done for ERIKA v2.x were derived. ERIKA Enterprise v2.x then was ported on a number of multicore microcontrollers, including:
- Altera Nios II;
- NXP PowerPC (Fado, Leopard, Cobra55), ST Microelectronics K2;
- Infineon Tricore AURIX.
The multi-core support in ERIKA2 has three main characteristics which are different from the now mainline AUTOSAR OS standard specification (which came out 8 years later):
- Spin-locks are queuing spin locks, using the G-T  algorithm (AUTOSAR spin-locks are without policy as of version 4.3 of AUTOSAR). This method has been independently proven to be the best one for real-time systems in  and .
- Resources are local or global depending on the code partitioning (AUTOSAR has two different APIs for Resources and Spin locks, and this is normal as code partitioning is handled at higher level inside the AUTOSAR RTE).
- Interprocessor interrupts are treated as asynchronous notifications, versus the synchronous (=slower) implementation mandated by AUTOSAR (note that both versions have been implemented in ERIKA Enterprise under the name of RN and RPC subsystems).
 Gary Graunke and Shreekant Thakkar. Synchronization Algorithms for SharedMemory Multiprocessors. IEEE Computer, 23(6):60-69, June 1990.
 A. Wieder and B. Brandenburg, “On Spin Locks in AUTOSAR: Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks”, Proceedings of the 34th IEEE Real-Time Systems Symposium (RTSS 2013), pp. 45–56, December 2013.
 A. Biondi and B. Brandenburg, “Lightweight Real-Time Synchronization under P-EDF on Symmetric and Asymmetric Multiprocessors”,Proceedings of the 28th Euromicro Conference on Real-Time Systems (ECRTS 2016), pp. 39–49, July 2016.
Multi- and Many- core support in ERIKA v3
After the first multicore implementations with ERIKA Enterprise v2.x, we noticed a continuous availability of multi-core embedded chips.
Therefore, thanks to the P-SOCRATES FP7 EU Project, starting from year 2014, we have started the development of what is now called ERIKA v3.
ERIKA v3 has been natively built with multi- and many- core CPU support in mind. In particular, among the features of version 3, we highlight:
- Single image kernel shared among the various CPUs;
- Support for partitioned and for global scheduling on multicores;
- Interprocessor Interrupts and Spin Locks;
- Lightweight OpenMP implementation support;
- Support for Hypervisors such as JailHouse;
- Designed for implementing AUTOSAR OS specifications regarding Memory Protection and Multicores.
The first version of ERIKA v3 for many-cores architectures has been released as part of the UpScale SDK. In this environment, ERIKA v3 was the base RTOS on top of which a minimal predictable OpenMP runtime was built, running on a 16-cpu cluster of a Kalray MPPA many-core.
Later versions of ERIKA Enterprise added support for common multi-core chips such as:
- ARM64 Cortex A5x, with support for NVidia Tegra X1 and Xilinx Ultrascale+ (thanks to the HERCULES H2020 EU project);
- Intel x64 (thanks to the Eurostars RETINA Project);
- Infineon Tricore AURIX.