Difference between revisions of "ARM Cortex-M"
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* CPUs | * CPUs | ||
** [https://www.arm.com/products/processors/cortex-m4-processor.php ARM Cortex-M4] | ** [https://www.arm.com/products/processors/cortex-m4-processor.php ARM Cortex-M4] | ||
+ | ** [https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m7 ARM Cortex-M7] | ||
* Microcontrollers | * Microcontrollers | ||
** [http://www.st.com/en/microcontrollers/stm32f4-series.html?querycriteria=productId=SS1577 ST STM32F4] Family | ** [http://www.st.com/en/microcontrollers/stm32f4-series.html?querycriteria=productId=SS1577 ST STM32F4] Family | ||
*** [http://www.st.com/en/microcontrollers/stm32f407vg.html STM32F407VGT6] specific MCU | *** [http://www.st.com/en/microcontrollers/stm32f407vg.html STM32F407VGT6] specific MCU | ||
*** [https://www.st.com/en/microcontrollers-microprocessors/stm32f429zi.html STM32F429ZIT6] specific MCU ''(currently only supported in a special version done for the Huawei University Challenge)'' | *** [https://www.st.com/en/microcontrollers-microprocessors/stm32f429zi.html STM32F429ZIT6] specific MCU ''(currently only supported in a special version done for the Huawei University Challenge)'' | ||
+ | ** [https://www.st.com/en/microcontrollers-microprocessors/stm32h7-series.html ST STM32H7] Family | ||
+ | *** [https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h753xi.html STM32H753XI] specific MCU | ||
** [https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M NXP i.MX8M] Family | ** [https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M NXP i.MX8M] Family | ||
*** i.MX8MQ6 specific MCU | *** i.MX8MQ6 specific MCU | ||
Line 25: | Line 28: | ||
** [http://www.st.com/en/evaluation-tools/stm32f4discovery.html ST STM32F4DISCOVERY] | ** [http://www.st.com/en/evaluation-tools/stm32f4discovery.html ST STM32F4DISCOVERY] | ||
** [https://www.st.com/en/evaluation-tools/32f429idiscovery.html ST STM32F429I-DISC1] ''(currently only supported in a special version done for the Huawei University Challenge)'' | ** [https://www.st.com/en/evaluation-tools/32f429idiscovery.html ST STM32F429I-DISC1] ''(currently only supported in a special version done for the Huawei University Challenge)'' | ||
+ | ** [https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-eval-boards/stm32h753i-eval.html STM32H753I-EVAL] | ||
** [https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/evaluation-kit-for-the-i.mx-8m-applications-processor:MCIMX8M-EVK NXP MCIMX8M-EVK] | ** [https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/evaluation-kit-for-the-i.mx-8m-applications-processor:MCIMX8M-EVK NXP MCIMX8M-EVK] | ||
** [https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/s32-automotive-platform/s32k144-evaluation-board:S32K144EVB NXP S32K144EVB] | ** [https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/s32-automotive-platform/s32k144-evaluation-board:S32K144EVB NXP S32K144EVB] | ||
Line 121: | Line 125: | ||
=== MODEL === | === MODEL === | ||
− | '''MODEL''' attribute of '''CPU_DATA''' supports | + | '''MODEL''' attribute of '''CPU_DATA''' supports the '''M4''', '''M4F''', '''M7''' and '''M7F''' values. |
Deafult value is '''M4'''. | Deafult value is '''M4'''. | ||
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==== FPU Support ==== | ==== FPU Support ==== | ||
− | Selecting '''M4F''' in the '''MODEL''' attribute of '''CPU_DATA''' the FPU support is enabled by default. | + | Selecting '''M4F''' or '''M7F''' in the '''MODEL''' attribute of '''CPU_DATA''' the FPU support is enabled by default. |
− | To disable the FPU support the '''DISABLE_FPU''' sub-field of '''M4F''' model SHALL be se to '''TRUE''' as shown in the following example: | + | To disable the FPU support the '''DISABLE_FPU''' sub-field of '''M4F'''/'''M7F''' model SHALL be se to '''TRUE''' as shown in the following example: |
CPU_DATA = CORTEX_M { | CPU_DATA = CORTEX_M { | ||
Line 233: | Line 237: | ||
*'''S32K1XX''': NXP S32K1xx Family | *'''S32K1XX''': NXP S32K1xx Family | ||
*'''STM32F4''': ST STM32F4 Family | *'''STM32F4''': ST STM32F4 Family | ||
+ | *'''STM32H7''': ST STM32H7 Family | ||
Example of a MCU_DATA section: | Example of a MCU_DATA section: | ||
Line 250: | Line 255: | ||
**'''STM32F407XX''' (default) | **'''STM32F407XX''' (default) | ||
**'''STM32F429XX''' ''(currently only supported in a special version done for the Huawei University Challenge)'' | **'''STM32F429XX''' ''(currently only supported in a special version done for the Huawei University Challenge)'' | ||
+ | *'''STM32H7''': ST STM32H7 Family | ||
+ | **'''STM32H753XX''' (default) | ||
Example of MODEL attribute of a MCU_DATA section: | Example of MODEL attribute of a MCU_DATA section: | ||
Line 269: | Line 276: | ||
*'''STM32F4''': ST STM32F4 Family | *'''STM32F4''': ST STM32F4 Family | ||
**'''STM32F407XX''' | **'''STM32F407XX''' | ||
− | *** | + | ***'''STM32F4_DISCOVERY''' |
**'''STM32F429XX''' | **'''STM32F429XX''' | ||
− | ***'''' | + | ***'''STM32F429I_DISC1''' |
+ | **'''STM32H753XX''' | ||
+ | ***'''STM32H753I_EVAL2''' | ||
Default value is '''NO_BOARD'''. | Default value is '''NO_BOARD'''. | ||
Line 638: | Line 647: | ||
*<code>LTDC_ER</code>: LTDC global Error interrupt | *<code>LTDC_ER</code>: LTDC global Error interrupt | ||
*<code>DMA2D</code>: DMA2D global interrupt | *<code>DMA2D</code>: DMA2D global interrupt | ||
+ | |||
+ | ==== STM32H7XX Family ==== | ||
+ | |||
+ | The '''STM32H7XX''' family microcontrollers has an interrupt vector table which could be stored in the flash or in RAM. The complete list of '''SOURCE''' entries is shown below. | ||
+ | |||
+ | *<code>WWDG</code>: Window WatchDog | ||
+ | *<code>PVD_AVD</code>: PVD/AVD through EXTI Line detection | ||
+ | *<code>TAMP_STAMP</code>: Tamper and TimeStamps through the EXTI line | ||
+ | *<code>RTC_WKUP</code>: RTC Wakeup through the EXTI line | ||
+ | *<code>FLASH</code>: FLASH | ||
+ | *<code>RCC</code>: RCC | ||
+ | *<code>EXTI0</code>: EXTI Line0 | ||
+ | *<code>EXTI1</code>: EXTI Line1 | ||
+ | *<code>EXTI2</code>: EXTI Line2 | ||
+ | *<code>EXTI3</code>: EXTI Line3 | ||
+ | *<code>EXTI4</code>: EXTI Line4 | ||
+ | *<code>DMA1_Stream0</code>: DMA1 Stream 0 | ||
+ | *<code>DMA1_Stream1</code>: DMA1 Stream 1 | ||
+ | *<code>DMA1_Stream2</code>: DMA1 Stream 2 | ||
+ | *<code>DMA1_Stream3</code>: DMA1 Stream 3 | ||
+ | *<code>DMA1_Stream4</code>: DMA1 Stream 4 | ||
+ | *<code>DMA1_Stream5</code>: DMA1 Stream 5 | ||
+ | *<code>DMA1_Stream6</code>: DMA1 Stream 6 | ||
+ | *<code>ADC</code>: ADC1, ADC2 and ADC3s | ||
+ | *<code>FDCAN1_IT0</code>: FDCAN1 interrupt line 0 | ||
+ | *<code>FDCAN2_IT0</code>: FDCAN2 interrupt line 0 | ||
+ | *<code>FDCAN1_IT1</code>: FDCAN1 interrupt line 1 | ||
+ | *<code>FDCAN2_IT1</code>: FDCAN2 interrupt line 1 | ||
+ | *<code>EXTI9_5</code>: External Line[9:5]s | ||
+ | *<code>TIM1_BRK</code>: TIM1 Break interrupt | ||
+ | *<code>TIM1_UP</code>: TIM1 Update interrupt | ||
+ | *<code>TIM1_TRG_COM</code>: TIM1 Trigger and Commutation interrupt | ||
+ | *<code>TIM1_CC</code>: TIM1 Capture Compare | ||
+ | *<code>TIM2</code>: TIM2 | ||
+ | *<code>TIM3</code>: TIM3 | ||
+ | *<code>TIM4</code>: TIM4 | ||
+ | *<code>I2C1_EV</code>: I2C1 Event | ||
+ | *<code>I2C1_ER</code>: I2C1 Error | ||
+ | *<code>I2C2_EV</code>: I2C2 Event | ||
+ | *<code>I2C2_ER</code>: I2C2 Error | ||
+ | *<code>SPI1</code>: SPI1 | ||
+ | *<code>SPI2</code>: SPI2 | ||
+ | *<code>USART1</code>: USART1 | ||
+ | *<code>USART2</code>: USART2 | ||
+ | *<code>USART3</code>: USART3 | ||
+ | *<code>EXTI15_10</code>: External Line[15:10]s | ||
+ | *<code>RTC_Alarm</code>: RTC Alarm (A and B) through EXTI Line | ||
+ | *<code>TIM8_BRK_TIM12</code>: TIM8 Break and TIM12 | ||
+ | *<code>TIM8_UP_TIM13</code>: TIM8 Update and TIM13 | ||
+ | *<code>TIM8_TRG_COM_TIM14</code>: TIM8 Trigger and Commutation and TIM14 | ||
+ | *<code>TIM8_CC</code>: TIM8 Capture Compare | ||
+ | *<code>DMA1_Stream7</code>: DMA1 Stream7 | ||
+ | *<code>FMC</code>: FMC | ||
+ | *<code>SDMMC1</code>: SDMMC1 | ||
+ | *<code>TIM5</code>: TIM5 | ||
+ | *<code>SPI3</code>: SPI3 | ||
+ | *<code>UART4</code>: UART4 | ||
+ | *<code>UART5</code>: UART5 | ||
+ | *<code>TIM6_DAC</code>: TIM6 and DAC1&2 underrun errors | ||
+ | *<code>TIM7</code>: TIM7 | ||
+ | *<code>DMA2_Stream0</code>: DMA2 Stream 0 | ||
+ | *<code>DMA2_Stream1</code>: DMA2 Stream 1 | ||
+ | *<code>DMA2_Stream2</code>: DMA2 Stream 2 | ||
+ | *<code>DMA2_Stream3</code>: DMA2 Stream 3 | ||
+ | *<code>DMA2_Stream4</code>: DMA2 Stream 4 | ||
+ | *<code>ETH</code>: Ethernet | ||
+ | *<code>ETH_WKUP</code>: Ethernet Wakeup through EXTI line | ||
+ | *<code>FDCAN_CAL</code>: FDCAN calibration unit interrupt | ||
+ | *<code>DMA2_Stream5</code>: DMA2 Stream 5 | ||
+ | *<code>DMA2_Stream6</code>: DMA2 Stream 6 | ||
+ | *<code>DMA2_Stream7</code>: DMA2 Stream 7 | ||
+ | *<code>USART6</code>: USART6 | ||
+ | *<code>I2C3_EV</code>: I2C3 event | ||
+ | *<code>I2C3_ER</code>: I2C3 error | ||
+ | *<code>OTG_HS_EP1_OUT</code>: USB OTG HS End Point 1 Out | ||
+ | *<code>OTG_HS_EP1_IN</code>: USB OTG HS End Point 1 In | ||
+ | *<code>OTG_HS_WKUP</code>: USB OTG HS Wakeup through EXTI | ||
+ | *<code>OTG_HS</code>: USB OTG HS | ||
+ | *<code>DCMI</code>: DCMI | ||
+ | *<code>RNG</code>: Rng | ||
+ | *<code>FPU</code>: FPU | ||
+ | *<code>UART7</code>: UART7 | ||
+ | *<code>UART8</code>: UART8 | ||
+ | *<code>SPI4</code>: SPI4 | ||
+ | *<code>SPI5</code>: SPI5 | ||
+ | *<code>SPI6</code>: SPI6 | ||
+ | *<code>SAI1</code>: SAI1 | ||
+ | *<code>LTDC</code>: LTDC | ||
+ | *<code>LTDC_ER</code>: LTDC error | ||
+ | *<code>DMA2D</code>: DMA2D | ||
+ | *<code>SAI2</code>: SAI2 | ||
+ | *<code>QUADSPI</code>: QUADSPI | ||
+ | *<code>LPTIM1</code>: LPTIM1 | ||
+ | *<code>CEC</code>: HDMI_CEC | ||
+ | *<code>I2C4_EV</code>: I2C4 Event | ||
+ | *<code>I2C4_ER</code>: I2C4 Error | ||
+ | *<code>SPDIF_RX</code>: SPDIF_RX | ||
+ | *<code>OTG_FS_EP1_OUT</code>: USB OTG FS End Point 1 Out | ||
+ | *<code>OTG_FS_EP1_IN</code>: USB OTG FS End Point 1 In | ||
+ | *<code>OTG_FS_WKUP</code>: USB OTG FS Wakeup through EXTI | ||
+ | *<code>OTG_FS</code>: USB OTG FS | ||
+ | *<code>DMAMUX1_OVR</code>: DMAMUX1 Overrun interrupt | ||
+ | *<code>HRTIM1_Master</code>: HRTIM Master Timer global Interrupt | ||
+ | *<code>HRTIM1_TIMA</code>: HRTIM Timer A global Interrupt | ||
+ | *<code>HRTIM1_TIMB</code>: HRTIM Timer B global Interrupt | ||
+ | *<code>HRTIM1_TIMC</code>: HRTIM Timer C global Interrupt | ||
+ | *<code>HRTIM1_TIMD</code>: HRTIM Timer D global Interrupt | ||
+ | *<code>HRTIM1_TIME</code>: HRTIM Timer E global Interrupt | ||
+ | *<code>HRTIM1_FLT</code>: HRTIM Fault global Interrupt | ||
+ | *<code>DFSDM1_FLT0</code>: DFSDM Filter0 Interrupt | ||
+ | *<code>DFSDM1_FLT1</code>: DFSDM Filter1 Interrupt | ||
+ | *<code>DFSDM1_FLT2</code>: DFSDM Filter2 Interrupt | ||
+ | *<code>DFSDM1_FLT3</code>: DFSDM Filter3 Interrupt | ||
+ | *<code>SAI3</code>: SAI3 global Interrupt | ||
+ | *<code>SWPMI1</code>: Serial Wire Interface 1 global interrupt | ||
+ | *<code>TIM15</code>: TIM15 global Interrupt | ||
+ | *<code>TIM16</code>: TIM16 global Interrupt | ||
+ | *<code>TIM17</code>: TIM17 global Interrupt | ||
+ | *<code>MDIOS_WKUP</code>: MDIOS Wakeup Interrupt | ||
+ | *<code>MDIOS</code>: MDIOS global Interrupt | ||
+ | *<code>JPEG</code>: JPEG global Interrupt | ||
+ | *<code>MDMA</code>: MDMA global Interrupt | ||
+ | *<code>SDMMC2</code>: SDMMC2 global Interrupt | ||
+ | *<code>HSEM1</code>: HSEM1 global Interrupt | ||
+ | *<code>ADC3</code>: ADC3 global Interrupt | ||
+ | *<code>DMAMUX2_OVR</code>: DMAMUX Overrun interrupt | ||
+ | *<code>BDMA_Channel0</code>: BDMA Channel 0 global Interrupt | ||
+ | *<code>BDMA_Channel1</code>: BDMA Channel 1 global Interrupt | ||
+ | *<code>BDMA_Channel2</code>: BDMA Channel 2 global Interrupt | ||
+ | *<code>BDMA_Channel3</code>: BDMA Channel 3 global Interrupt | ||
+ | *<code>BDMA_Channel4</code>: BDMA Channel 4 global Interrupt | ||
+ | *<code>BDMA_Channel5</code>: BDMA Channel 5 global Interrupt | ||
+ | *<code>BDMA_Channel6</code>: BDMA Channel 6 global Interrupt | ||
+ | *<code>BDMA_Channel7</code>: BDMA Channel 7 global Interrupt | ||
+ | *<code>COMP1</code>: COMP1 global Interrupt | ||
+ | *<code>LPTIM2</code>: LP TIM2 global interrupt | ||
+ | *<code>LPTIM3</code>: LP TIM3 global interrupt | ||
+ | *<code>LPTIM4</code>: LP TIM4 global interrupt | ||
+ | *<code>LPTIM5</code>: LP TIM5 global interrupt | ||
+ | *<code>LPUART1</code>: LP UART1 interrupt | ||
+ | *<code>CRS</code>: Clock Recovery Global Interrupt | ||
+ | *<code>ECC</code>: ECC diagnostic Global Interrupt | ||
+ | *<code>SAI4</code>: SAI4 global interrupt | ||
+ | *<code>WAKEUP_PIN</code>: Interrupt for all 6 wake-up pins | ||
= OSEK/VDX Extensions = | = OSEK/VDX Extensions = |
Latest revision as of 16:08, 21 September 2020
Contents
Introduction
This manual describes the porting details of the ERIKA Enterprise v3 kernel(s) for families of microcontrollers which integrate ARM Cortex-M CPUs.
Cortex-M features supported
The following are the main features of the currently implemented support:
- Development tools
- CPUs
- Microcontrollers
- ST STM32F4 Family
- STM32F407VGT6 specific MCU
- STM32F429ZIT6 specific MCU (currently only supported in a special version done for the Huawei University Challenge)
- ST STM32H7 Family
- STM32H753XI specific MCU
- NXP i.MX8M Family
- i.MX8MQ6 specific MCU
- NXP S32K1xx Family
- S32K144 specific MCU
- S32K148 specific MCU
- ST STM32F4 Family
- Evaluation boards
- ST STM32F4DISCOVERY
- ST STM32F429I-DISC1 (currently only supported in a special version done for the Huawei University Challenge)
- STM32H753I-EVAL
- NXP MCIMX8M-EVK
- NXP S32K144EVB
- NXP S32K148EVB
- External Libraries
Additionally, we are porting ERIKA3 also on a ARM Cortex-M7 CPU on ST 32F746GDISCOVERY board with STM32F746NG MCU.
In the next months, the public code will be delivered through the GitHub repository. In case of urgent need, please contact us.
Tutorials
The following tutorials are available for this architecture:
- Cortex-M: NXP S32K1xx application build on Windows
- Cortex-M: NXP S32K1xx application debug with PEmicro OCD on Windows
- Cortex-M: ST STM32F4xx application build on Windows
- Cortex-M: ST STM32F4xx application debug with ST-Link OCD on Windows
Configuration and Programming
ERIKA Enterprise is configured through RT-Druid and an OIL file and some other properties.
The following sections describe the properties and OIL fields customized for ARM Cortex-M architecture.
GCC Compiler Path
It is possible to choose the path in three different ways:
- Specific environment variables: ARM_TOOLS
- E.g.: ARM_TOOLS=C:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q3
- RT-Druid Eclipse IDE Property.
- RT-Druid Configuration File Entry: preference_cortex_m__path_for_gcc_compiler
- E.g.: preference_cortex_m__path_for_gcc_compiler=C:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q3
Here is an example of RT-Druid configuration file.
S32 SDK Path
It is possible to choose the path in three different ways:
- Specific environment variables: S32_SDK_FILES
- E.g.: S32_SDK_FILES=C:\NXP\S32DS_ARM_v2.0\S32DS\S32SDK_S32K14x_EAR_0.8.4
- RT-Druid Eclipse IDE Property.
- RT-Druid Configuration File Entry: preference_cortex_m__path_for_s32_sdk
- E.g.: preference_cortex_m__path_for_s32_sdk=C:\NXP\S32DS_ARM_v2.0\S32DS\S32SDK_S32K14x_EAR_0.8.4
Here is an example of RT-Druid configuration file.
STM32F4 Cube Path
It is possible to choose the path in three different ways:
- Specific environment variables: STM32_CUBE_F4_FILES
- E.g.: STM32_CUBE_F4_FILES=C:\Evidence\STM32Cube_FW_F4_V1.25.0
- RT-Druid Eclipse IDE Property.
- RT-Druid Configuration File Entry: preference_cortex_m__path_for_stm32_cube_f4
- E.g.: preference_cortex_m__path_for_stm32_cube_f4=C:\Evidence\STM32Cube_FW_F4_V1.25.0
Here is an example of RT-Druid configuration file.
Lauterbach TRACE32 Path
It is possible to choose the path in two different ways:
- RT-Druid Eclipse IDE Property.
- RT-Druid Configuration File Entry: preference_lauterbach__path_for_trace32
- E.g.: preference_lauterbach__path_for_trace32=C:\T32
Here is an example of RT-Druid configuration file.
Lauterbach Emulator Interface
It is possible to choose the path in two different ways:
- RT-Druid Eclipse IDE Property.
- RT-Druid Configuration File Entry: preference_lauterbach__emulator_usb_interface
- E.g.: preference_lauterbach__emulator_usb_interface=true
Here is an example of RT-Druid configuration file.
CPU
CPU_DATA object must be set to CORTEX_M.
Example of a CPU_DATA section:
CPU_DATA = CORTEX_M { ... };
MODEL
MODEL attribute of CPU_DATA supports the M4, M4F, M7 and M7F values. Deafult value is M4.
Example of a MODEL attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; ... };
FPU Support
Selecting M4F or M7F in the MODEL attribute of CPU_DATA the FPU support is enabled by default.
To disable the FPU support the DISABLE_FPU sub-field of M4F/M7F model SHALL be se to TRUE as shown in the following example:
CPU_DATA = CORTEX_M { MODEL = M4F { DISABLE_FPU = TRUE; }; ... };
COMPILER
COMPILER attribute of CPU_DATA supports for now the GCC value only. Deafult value is GCC.
Example of a COMPILER attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; COMPILER = GCC; ... };
MINIMAL_OPTS
MINIMAL_OPTS boolean property of COMPILER attribute of CPU_DATA configures the build system with minimal compiling and linking options. That allow an user to specify it's own compiler and linker oprions via CFLAGS, CXXFLAGS and LDFLAGS. The default value is set to FALSE.
Example of a MINIMAL_OPTS property of COMPILER attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; COMPILER = GCC { MINIMAL_OPTS = TRUE; }; ... };
LINKER_SCRIPT
LINKER_SCRIPT boolean property of COMPILER attribute of CPU_DATA configures the build system to use an external linker script that SHALL be placed in the project root folder.
Example of a LINKER_SCRIPT property of COMPILER attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; COMPILER = GCC { LINKER_SCRIPT = "myLinkerScript.ld"; }; ... };
EXECUTE_FROM_RAM
EXECUTE_FROM_RAM attribute of CPU_DATA configures the build system generate binary to execute the application in RAM. The default value is set to FALSE.
Example of a COMPILER attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; EXECUTE_FROM_RAM = TRUE; ... };
TRACER
TRACER attribute of CPU_DATA configures the build system to generate Lauterbach TRACE32 scripts to enable the tracing support. This attribute make sense in the MCUs that implements ITM and/or ETM hardware. Supported values are OFF, SWO and OFFCHIP. The default value is set to OFF.
Example of a TRACER attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; TRACER = OFFCHIP; ... };
SYS_STACK_SIZE
SYS_STACK_SIZE attribute of CPU_DATA configures the size in bytes of the system stack. The default value is set to 1024.
Example of a TRACER attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; SYS_STACK_SIZE = 2048; ... };
MCU
MCU_DATA object supports for now only the followings MCUs:
- S32K1XX: NXP S32K1xx Family
- STM32F4: ST STM32F4 Family
- STM32H7: ST STM32H7 Family
Example of a MCU_DATA section:
MCU_DATA = S32K1XX { ... };
MODEL
MODEL attribute of MCU_DATA supports for now the followings models for every family of MCU:
- S32K1XX: NXP S32K1xx Family
- S32K144 (default)
- S32K148
- STM32F4: ST STM32F4 Family
- STM32F407XX (default)
- STM32F429XX (currently only supported in a special version done for the Huawei University Challenge)
- STM32H7: ST STM32H7 Family
- STM32H753XX (default)
Example of MODEL attribute of a MCU_DATA section:
MCU_DATA = S32K1XX { MODEL = S32K148; ... };
BOARD
BOARD_DATA object supports for now only the followings boards for every MCU
- S32K1XX: NXP S32K1xx Family
- S32K144
- S32K144EVB_Q100
- S32K148
- S32K148EVB_Q144_Q176
- S32K144
- STM32F4: ST STM32F4 Family
- STM32F407XX
- STM32F4_DISCOVERY
- STM32F429XX
- STM32F429I_DISC1
- STM32H753XX
- STM32H753I_EVAL2
- STM32F407XX
Default value is NO_BOARD.
Example of a BOARD_DATA section:
BOARD_DATA = S32K148EVB_Q144_Q176;
LIB
LIB object supports for now the followings libraries for every family of MCU:
- S32K1XX: NXP S32K1xx Family
- S32_SDK: S32SDK provided by S32 Design Studio IDE for Arm based MCUs
- STM32F4: ST STM32F4 Family
- STM32_CUBE_F4: STM32Cube MCU Package for STM32F4 series
Example of a LIB section:
LIB = S32_SDK { ... };
S32 SDK
The following sections describe the OIL fields of the LIB object customized for the official S32 SDK supports.
NOTE: The complete documentation of the S32SDK provided by S32 Design Studio IDE for Arm based MCUs is not part of ERIKA3.
NOTE: Please keep in mind that every time an user configures a driver or a module to use interrupts, a corresponding ISRs with correct relative source shall be defined in the OIL file to let ERIKA3 to correctly manage ISRs.
BOARD
BOARD attribute of S32_SDK supports for now only the followings boards for every MCU:
- S32K144
- S32K144EVB_Q100
- S32K148
- S32K148EVB_Q144_Q176
Default value is S32K144EVB_Q100.
Example of SDK_BOARD attribute of S32_SDK:
LIB = S32_SDK { BOARD = S32K148EVB_Q144_Q176; ... };
VERSION
VERSION attribute of S32_SDK supports for now the "0.8.4 EAR" and "0.8.6 EAR" value only.
Example of VERSION attribute of S32_SDK:
LIB = S32_SDK { BOARD = S32K148EVB_Q144_Q176; VERSION = "0.8.4 EAR"; ... };
STAND_ALONE
STAND_ALONE boolean attribute of S32_SDK configures the build system to generate or not libs32sdk.a stand-alone binary library. The default value is set to TRUE. Default value is TRUE.
Example of STAND_ALONE attribute of S32_SDK:
LIB = S32_SDK { BOARD = S32K148EVB_Q144_Q176; VERSION = "0.8.4 EAR"; STAND_ALONE = TRUE; };
STM32 CUBE F4
The following sections describe the OIL fields of the LIB object customized for the official STM32 CUBE F4 supports.
NOTE: The complete documentation of the STM32Cube MCU Package for STM32F4 series is not part of ERIKA3.
NOTE: Please keep in mind that every time an user configures a driver or a module to use interrupts, a corresponding ISRs with correct relative source shall be defined in the OIL file to let ERIKA3 to correctly manage ISRs.
BOARD
BOARD attribute of STM32_CUBE_F4 supports for now only the followings boards for every MCU:
- STM32F407XX
- STM32F4_DISCOVERY
- STM32F429XX
- STM32F429I_DISC1
Example of SDK_BOARD attribute of STM32_CUBE_F4:
LIB = STM32_CUBE_F4 { BOARD = STM32F429I_DISC1; ... };
VERSION
VERSION attribute of STM32_CUBE_F4 supports for now the "1.18.0", "1.24.0" and "1.25.0" values only.
Example of VERSION attribute of STM32_CUBE_F4:
LIB = STM32_CUBE_F4 { BOARD = STM32F429I_DISC1; VERSION = "1.25.0"; ... };
STAND_ALONE
STAND_ALONE boolean attribute of STM32_CUBE_F4 configures the build system to generate or not libstm32cubef4.a stand-alone binary library. The default value is set to TRUE.
Example of STAND_ALONE attribute of STM32_CUBE_F4:
LIB = STM32_CUBE_F4 { BOARD = STM32F429I_DISC1; VERSION = "1.25.0"; STAND_ALONE = TRUE; };
Interrupt Handling
Traps
ARM Cortex-M CPU has followings default traps that could be used as SOURCE in the ISRs configuration of ERIKA3.
-
NMI
: Non-maskable Interrupt (NMI) Trap -
HARD_FAULT
: Hard Fault Trap -
BUS_FAULT
: Bus Fault Trap -
USAGE_FAULT
: Usage Fault Trap -
DEBUG_MONITOR
: Debug Monitor Trap -
SYSTICK
: SysTick Trap
Interrupts
The Interrupt Handling support is microcontroller dependent. For each supported microcontroller family, the ISRs configuration of ERIKA3 is shown below.
S32K1XX Family
The S32K1XX family microcontrollers has an interrupt vector table which could be stored in the flash or in RAM. The complete list of SOURCE entries is shown below.
-
DMA0
: DMA channel 0 transfer complete -
DMA1
: DMA channel 1 transfer complete -
DMA2
: DMA channel 2 transfer complete -
DMA3
: DMA channel 3 transfer complete -
DMA4
: DMA channel 4 transfer complete -
DMA5
: DMA channel 5 transfer complete -
DMA6
: DMA channel 6 transfer complete -
DMA7
: DMA channel 7 transfer complete -
DMA8
: DMA channel 8 transfer complete -
DMA9
: DMA channel 9 transfer complete -
DMA10
: DMA channel 10 transfer complete -
DMA11
: DMA channel 11 transfer complete -
DMA12
: DMA channel 12 transfer complete -
DMA13
: DMA channel 13 transfer complete -
DMA14
: DMA channel 14 transfer complete -
DMA15
: DMA channel 15 transfer complete -
DMA_ERR
: DMA error interrupt channels 0-15 -
MCM_FPU
: FPU sources -
FTFC_CMD
: FTFC Command complete -
FTFC_RDC
: FTFC Read collision -
PMC_LVD
: PMC Low voltage detect interrupt -
FTFC_FAULT
: FTFC Double bit fault detect -
WDOG_EVM
: Single interrupt vector for WDOG and EWM -
RCM
: RCM Asynchronous Interrupt -
LPI2C0_MASTER
:LPI2C0 Master Interrupt -
LPI2C0_SLAVE
: LPI2C0 Slave Interrupt -
LPSPI0
: LPSPI0 Interrupt -
LPSPI1
: LPSPI1 Interrupt -
LPSPI2
: LPSPI2 Interrupt -
LPI2C1_MASTER
:LPI2C1 Master Interrup -
LPI2C1_SLAVE
: LPI2C1 Slave Interrupt -
LPUART0
: LPUART0 Transmit -
LPUART1
: LPUART1 Transmit -
LPUART2
: LPUART2 Transmit -
ADC0
: ADC0 interrupt request -
ADC1
: ADC1 interrupt request -
CMP0
: CMP0 interrupt request -
ERM_SINGLE
: ERM single bit error correction -
ERM_DOUBLE
: ERM double bit error non-correctable -
RTC_ALARM
: RTC alarm interrupt -
RTC_SECONDS
: RTC seconds interrupt -
LPIT0_CH0
: LPIT0 channel 0 overflow interrupt -
LPIT0_CH1
: LPIT0 channel 1 overflow interrupt -
LPIT0_CH2
: LPIT0 channel 2 overflow interrupt -
LPIT0_CH3
: LPIT0 channel 3 overflow interrupt -
PDB0
: PDB0 interrupt -
SAI1_TX
: SAI1 Transmit Synchronous interrupt -
SAI1_RX
: SAI1 Receive Synchronous interrupt -
SCG
: SCG bus interrupt request -
LPTMR0
: LPTIMER0 interrupt request -
PORTA
: Port A pin detect interrupt -
PORTB
: Port B pin detect interrupt -
PORTC
: Port C pin detect interrupt -
PORTD
: Port D pin detect interrupt -
PORTE
: Port E pin detect interrupt -
SWI
: Software interrupt -
QSPI0
: QSPI All interrupts ORed output -
PDB1
: PDB1 interrupt -
FLEXIO
: FlexIO Interrupt -
SAI0_TX
: SAI0 Transmit Synchronous interrupt -
SAI0_RX
: SAI0 Receive Synchronous interrupt -
ENET_TIMER
: ENET 1588 Timer Interrupt - synchronous -
ENET_TX
: ENET Data transfer done -
ENET_RX
: ENET Receive Buffer Done for Ring/Queue 0 -
ENET_ERR
: ENET Payload receive error -
ENET_STOP
: ENET Graceful stop -
ENET_WAKE
: ENET Wake from sleep -
CAN0_ORED
: CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] -
CAN0_ERR
: CAN0 Interrupt indicating that errors were detected on the CAN bus -
CAN0_WAKE
: CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode -
CAN0_ORED_0_15
: CAN0 OR'ed Message buffer (0-15) -
CAN0_ORED_16_31
: CAN0 OR'ed Message buffer (16-31) -
CAN1_ORED
: CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] -
CAN1_ERR
: CAN1 Interrupt indicating that errors were detected on the CAN bus -
CAN1_ORED_0_15
: CAN1 OR'ed Message buffer (0-15) -
CAN1_ORED_16_31
: CAN0 OR'ed Message buffer (16-31) -
CAN2_ORED
: CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] -
CAN2_ERR
: CAN0 Interrupt indicating that errors were detected on the CAN bus -
CAN2_ORED_0_15
: CAN1 OR'ed Message buffer (0-15) -
CAN2_ORED_16_31
: CAN0 OR'ed Message buffer (16-31) -
FTM0_CH0_CH1
: FTM0 Channel 0 and 1 interrupt -
FTM0_CH2_CH3
: FTM0 Channel 2 and 3 interrupt -
FTM0_CH4_CH5
: FTM0 Channel 4 and 5 interrupt -
FTM0_CH6_CH7
: FTM0 Channel 6 and 7 interrupt -
FTM0_FAULT
: FTM0 Fault interrupt -
FTM0_OVF_RELOAD
: FTM0 Counter overflow and Reload interrupt -
FTM1_CH0_CH1
: FTM1 Channel 0 and 1 interrupt -
FTM1_CH2_CH3
: FTM1 Channel 2 and 3 interrupt -
FTM1_CH4_CH5
: FTM1 Channel 4 and 5 interrupt -
FTM1_CH6_CH7
: FTM1 Channel 6 and 7 interrupt -
FTM1_FAULT
: FTM1 Fault interrupt -
FTM1_OVF_RELOAD
: FTM1 Counter overflow and Reload interrupt -
FTM2_CH0_CH1
: FTM2 Channel 0 and 1 interrupt -
FTM2_CH2_CH3
: FTM2 Channel 2 and 3 interrupt -
FTM2_CH4_CH5
: FTM2 Channel 4 and 5 interrupt -
FTM2_CH6_CH7
: FTM2 Channel 6 and 7 interrupt -
FTM2_FAULT
: FTM2 Fault interrupt -
FTM2_OVF_RELOAD
: FTM2 Counter overflow and Reload interrupt -
FTM3_CH0_CH1
: FTM3 Channel 0 and 1 interrupt -
FTM3_CH2_CH3
: FTM3 Channel 2 and 3 interrupt -
FTM3_CH4_CH5
: FTM3 Channel 4 and 5 interrupt -
FTM3_CH6_CH7
: FTM3 Channel 6 and 7 interrupt -
FTM3_FAULT
: FTM3 Fault interrupt -
FTM3_OVF_RELOAD
: FTM3 Counter overflow and Reload interrupt -
FTM4_CH0_CH1
: FTM4 Channel 0 and 1 interrupt -
FTM4_CH2_CH3
: FTM4 Channel 2 and 3 interrupt -
FTM4_CH4_CH5
: FTM4 Channel 4 and 5 interrupt -
FTM4_CH6_CH7
: FTM4 Channel 6 and 7 interrupt -
FTM4_FAULT
: FTM4 Fault interrupt -
FTM4_OVF_RELOAD
: FTM4 Counter overflow and Reload interrupt -
FTM5_CH0_CH1
: FTM5 Channel 0 and 1 interrupt -
FTM5_CH2_CH3
: FTM5 Channel 2 and 3 interrupt -
FTM5_CH4_CH5
: FTM5 Channel 4 and 5 interrupt -
FTM5_CH6_CH7
: FTM5 Channel 6 and 7 interrupt -
FTM5_FAULT
: FTM5 Fault interrupt -
FTM5_OVF_RELOAD
: FTM5 Counter overflow and Reload interrupt -
FTM6_CH0_CH1
: FTM6 Channel 0 and 1 interrupt -
FTM6_CH2_CH3
: FTM6 Channel 2 and 3 interrupt -
FTM6_CH4_CH5
: FTM6 Channel 4 and 5 interrupt -
FTM6_CH6_CH7
: FTM6 Channel 6 and 7 interrupt -
FTM6_FAULT
: FTM6 Fault interrupt -
FTM6_OVF_RELOAD
: FTM6 Counter overflow and Reload interrupt -
FTM7_CH0_CH1
: FTM7 Channel 0 and 1 interrupt -
FTM7_CH2_CH3
: FTM7 Channel 2 and 3 interrupt -
FTM7_CH4_CH5
: FTM7 Channel 4 and 5 interrupt -
FTM7_CH6_CH7
: FTM7 Channel 6 and 7 interrupt -
FTM7_FAULT
: FTM7 Fault interrupt -
FTM7_OVF_RELOAD
: FTM7 Counter overflow and Reload interrupt
STM32F4XX Family
The STM32F4XX family microcontrollers has an interrupt vector table which could be stored in the flash or in RAM. The complete list of SOURCE entries is shown below.
WWDG
: Window Watchdog interruptPVD
: PVD through EXTI line detection interruptTAMP_STAMP
: Tamper and TimeStamp interrupts through the EXTI lineRTC_WKUP
: RTC Wakeup interrupt through the EXTI lineFLASH
: Flash global interruptRCC
: RCC global interruptEXTI0
: EXTI Line0 interruptEXTI1
: EXTI Line1 interruptEXTI2
: EXTI Line2 interruptEXTI3
: EXTI Line3 interruptEXTI4
: EXTI Line4 interruptDMA1_S0
: DMA1 Stream0 global interruptDMA1_S1
: DMA1 Stream1 global interruptDMA1_S2
: DMA1 Stream2 global interruptDMA1_S3
: DMA1 Stream3 global interruptDMA1_S4
: DMA1 Stream4 global interruptDMA1_S5
: DMA1 Stream5 global interruptDMA1_S6
: DMA1 Stream6 global interruptADC
: ADC1, ADC2 and ADC3 global interruptsCAN1_TX
: CAN1 TX interruptsCAN1_RX0
: CAN1 RX0 interruptsCAN1_RX1
: CAN1 RX1 interruptCAN1_SCE
: CAN1 SCE interruptEXTI9_5
: EXTI Line[9:5] interruptsTIM1_BRK_TIM9
: TIM1 Break interrupt and TIM9 global interruptTIM1_UP_TIM10
: TIM1 Update interrupt and TIM10 global interruptTIM1_TRG_COM_TIM11
: TIM1 Trigger and Commutation interrupts and TIM11 global interruptTIM1_CC
: TIM1 Capture Compare interruptTIM2
: TIM2 global interruptTIM3
: TIM3 global interruptTIM4
: TIM4 global interruptI2C1_EV
: I2C1 event interruptI2C1_ER
: I2C1 error interruptI2C2_EV
: I2C2 event interruptI2C2_ER
: I2C2 error interruptSPI1
: SPI1 global interruptSPI2
: SPI2 global interruptUSART1
: USART1 global interruptUSART2
: USART2 global interruptUSART3
: USART3 global interruptEXTI15_10
: EXTI Line[15:10] interruptsRTC_ALARM
: RTC Alarms (A and B) through EXTI line interruptOTG_FS_WKUP
: USB On-The-Go FS Wakeup through EXTI line interruptTIM8_BRK_TIM12
: TIM8 Break interrupt and TIM12 global interruptTIM8_UP_TIM13
: TIM8 Update interrupt and TIM13 global interruptTIM8_TRG_COM_TIM1
: TIM8 Trigger and Commutation interrupts and TIM14 global interruptTIM8_CC
: TIM8 Capture Compare interruptDMA1_S7
: DMA1 Stream7 global interruptFSMC
: FSMC global interruptSDIO
: SDIO global interruptTIM5
: TIM5 global interruptSPI3
: SPI3 global interruptUART4
: UART4 global interruptUART5
: UART5 global interruptTIM6_DAC
: TIM6 global interrupt, DAC1 and DAC2 underrun error interruptsTIM7
: TIM7 global interruptDMA2_S0
: DMA2 Stream0 global interruptDMA2_S1
: DMA2 Stream1 global interruptDMA2_S2
: DMA2 Stream2 global interruptDMA2_S3
: DMA2 Stream3 global interruptDMA2_S4
: DMA2 Stream4 global interruptETH
: Ethernet global interruptETH_WKUP
: Ethernet Wakeup through EXTI line interruptCAN2_TX
: CAN2 TX interruptsCAN2_RX0
: CAN2 RX0 interruptsCAN2_RX1
: CAN2 RX1 interruptCAN2_SCE
: CAN2 SCE interruptOTG_FS
: USB On The Go FS global interruptDMA2_S5
: DMA2 Stream5 global interruptDMA2_S6
: DMA2 Stream6 global interruptDMA2_S7
: DMA2 Stream7 global interruptUSART6
: USART6 global interruptI2C3_EV
: I2C3 event interruptI2C3_ER
: I2C3 error interruptOTG_HS_EP1_OUT
: USB On The Go HS End Point 1 Out global interruptOTG_HS_EP1_IN
: USB On The Go HS End Point 1 In global interruptOTG_HS_WKUP
: USB On The Go HS Wakeup through EXTI interruptOTG_HS USB
: On The Go HS global interruptDCMI
: DCMI global interruptCRYP
: CRYP crypto global interruptHASH_RNG
: Hash and Rng global interruptFPU
: FPU global interruptUART7
: UART 7 global interruptUART8
: UART 8 global interruptSPI4
: SPI 4 global interruptSPI5
: SPI 5 global interruptSPI6
: SPI 6 global interruptSAI1
: SAI1 global interruptLTDC
: LTDC global interruptLTDC_ER
: LTDC global Error interruptDMA2D
: DMA2D global interrupt
STM32H7XX Family
The STM32H7XX family microcontrollers has an interrupt vector table which could be stored in the flash or in RAM. The complete list of SOURCE entries is shown below.
WWDG
: Window WatchDogPVD_AVD
: PVD/AVD through EXTI Line detectionTAMP_STAMP
: Tamper and TimeStamps through the EXTI lineRTC_WKUP
: RTC Wakeup through the EXTI lineFLASH
: FLASHRCC
: RCCEXTI0
: EXTI Line0EXTI1
: EXTI Line1EXTI2
: EXTI Line2EXTI3
: EXTI Line3EXTI4
: EXTI Line4DMA1_Stream0
: DMA1 Stream 0DMA1_Stream1
: DMA1 Stream 1DMA1_Stream2
: DMA1 Stream 2DMA1_Stream3
: DMA1 Stream 3DMA1_Stream4
: DMA1 Stream 4DMA1_Stream5
: DMA1 Stream 5DMA1_Stream6
: DMA1 Stream 6ADC
: ADC1, ADC2 and ADC3sFDCAN1_IT0
: FDCAN1 interrupt line 0FDCAN2_IT0
: FDCAN2 interrupt line 0FDCAN1_IT1
: FDCAN1 interrupt line 1FDCAN2_IT1
: FDCAN2 interrupt line 1EXTI9_5
: External Line[9:5]sTIM1_BRK
: TIM1 Break interruptTIM1_UP
: TIM1 Update interruptTIM1_TRG_COM
: TIM1 Trigger and Commutation interruptTIM1_CC
: TIM1 Capture CompareTIM2
: TIM2TIM3
: TIM3TIM4
: TIM4I2C1_EV
: I2C1 EventI2C1_ER
: I2C1 ErrorI2C2_EV
: I2C2 EventI2C2_ER
: I2C2 ErrorSPI1
: SPI1SPI2
: SPI2USART1
: USART1USART2
: USART2USART3
: USART3EXTI15_10
: External Line[15:10]sRTC_Alarm
: RTC Alarm (A and B) through EXTI LineTIM8_BRK_TIM12
: TIM8 Break and TIM12TIM8_UP_TIM13
: TIM8 Update and TIM13TIM8_TRG_COM_TIM14
: TIM8 Trigger and Commutation and TIM14TIM8_CC
: TIM8 Capture CompareDMA1_Stream7
: DMA1 Stream7FMC
: FMCSDMMC1
: SDMMC1TIM5
: TIM5SPI3
: SPI3UART4
: UART4UART5
: UART5TIM6_DAC
: TIM6 and DAC1&2 underrun errorsTIM7
: TIM7DMA2_Stream0
: DMA2 Stream 0DMA2_Stream1
: DMA2 Stream 1DMA2_Stream2
: DMA2 Stream 2DMA2_Stream3
: DMA2 Stream 3DMA2_Stream4
: DMA2 Stream 4ETH
: EthernetETH_WKUP
: Ethernet Wakeup through EXTI lineFDCAN_CAL
: FDCAN calibration unit interruptDMA2_Stream5
: DMA2 Stream 5DMA2_Stream6
: DMA2 Stream 6DMA2_Stream7
: DMA2 Stream 7USART6
: USART6I2C3_EV
: I2C3 eventI2C3_ER
: I2C3 errorOTG_HS_EP1_OUT
: USB OTG HS End Point 1 OutOTG_HS_EP1_IN
: USB OTG HS End Point 1 InOTG_HS_WKUP
: USB OTG HS Wakeup through EXTIOTG_HS
: USB OTG HSDCMI
: DCMIRNG
: RngFPU
: FPUUART7
: UART7UART8
: UART8SPI4
: SPI4SPI5
: SPI5SPI6
: SPI6SAI1
: SAI1LTDC
: LTDCLTDC_ER
: LTDC errorDMA2D
: DMA2DSAI2
: SAI2QUADSPI
: QUADSPILPTIM1
: LPTIM1CEC
: HDMI_CECI2C4_EV
: I2C4 EventI2C4_ER
: I2C4 ErrorSPDIF_RX
: SPDIF_RXOTG_FS_EP1_OUT
: USB OTG FS End Point 1 OutOTG_FS_EP1_IN
: USB OTG FS End Point 1 InOTG_FS_WKUP
: USB OTG FS Wakeup through EXTIOTG_FS
: USB OTG FSDMAMUX1_OVR
: DMAMUX1 Overrun interruptHRTIM1_Master
: HRTIM Master Timer global InterruptHRTIM1_TIMA
: HRTIM Timer A global InterruptHRTIM1_TIMB
: HRTIM Timer B global InterruptHRTIM1_TIMC
: HRTIM Timer C global InterruptHRTIM1_TIMD
: HRTIM Timer D global InterruptHRTIM1_TIME
: HRTIM Timer E global InterruptHRTIM1_FLT
: HRTIM Fault global InterruptDFSDM1_FLT0
: DFSDM Filter0 InterruptDFSDM1_FLT1
: DFSDM Filter1 InterruptDFSDM1_FLT2
: DFSDM Filter2 InterruptDFSDM1_FLT3
: DFSDM Filter3 InterruptSAI3
: SAI3 global InterruptSWPMI1
: Serial Wire Interface 1 global interruptTIM15
: TIM15 global InterruptTIM16
: TIM16 global InterruptTIM17
: TIM17 global InterruptMDIOS_WKUP
: MDIOS Wakeup InterruptMDIOS
: MDIOS global InterruptJPEG
: JPEG global InterruptMDMA
: MDMA global InterruptSDMMC2
: SDMMC2 global InterruptHSEM1
: HSEM1 global InterruptADC3
: ADC3 global InterruptDMAMUX2_OVR
: DMAMUX Overrun interruptBDMA_Channel0
: BDMA Channel 0 global InterruptBDMA_Channel1
: BDMA Channel 1 global InterruptBDMA_Channel2
: BDMA Channel 2 global InterruptBDMA_Channel3
: BDMA Channel 3 global InterruptBDMA_Channel4
: BDMA Channel 4 global InterruptBDMA_Channel5
: BDMA Channel 5 global InterruptBDMA_Channel6
: BDMA Channel 6 global InterruptBDMA_Channel7
: BDMA Channel 7 global InterruptCOMP1
: COMP1 global InterruptLPTIM2
: LP TIM2 global interruptLPTIM3
: LP TIM3 global interruptLPTIM4
: LP TIM4 global interruptLPTIM5
: LP TIM5 global interruptLPUART1
: LP UART1 interruptCRS
: Clock Recovery Global InterruptECC
: ECC diagnostic Global InterruptSAI4
: SAI4 global interruptWAKEUP_PIN
: Interrupt for all 6 wake-up pins
OSEK/VDX Extensions
This Section contains information about the OSEK/VDX Extensions (or optional features) that have been implemented for the Arm Cortex-M support.
System Timer
System Timer counter is implemented using SysTick of Cortex-M CPUso the DEVICE attribute MUST be se to SYSTICK as shown below.
Example of a System Timer counter:
COUNTER SystemTimer { MINCYCLE = 1; MAXALLOWEDVALUE = 65535; TICKSPERBASE = 1; TYPE = HARDWARE { DEVICE = "SYSTICK"; SYSTEM_TIMER = TRUE; }; SECONDSPERTICK = 0.001; };
CPU_CLOCK
System Timer need the CPU_CLOCK attribute of CPU_DATA. This value, expressed as MHz, must be set to the configured frequency of the CPU.
Example of a CPU_CLOCK attribute of CPU_DATA section:
CPU_DATA = CORTEX_M { MODEL = M4; CPU_CLOCK = 48.0; ... };