e200 INTC prio LIFO not popped (INTC_EOIR not written)
Posted: Mon Sep 02, 2013 3:20 pm
Dear EE users, community,
I have experimented with the EE kernel om my MPC5643L devboard, with great appreciation of the incredible work, efficiency and easy of use of the EE RTOS.
I started from a demo generated by Eclipse, using ISR_dynamic_table.
However, my application needs the least ISR jitter possible. As we are running a very time critical ISR. (just 2 time critical isrs, the rest is less time critical).
Therefor, I converted my conf.oil to use static interrupt table.
Howver, then I get following problem: The ISR fires only once, then never again. Looking at INTC_CPR, I see it is "stuck" at 7, which is the ISR priority of my interrupt that fired once. This is typical, when the priority LIFO of the INTC did not get popped.
Looking at ee_irq.c in pkg/cpu/e200zx/src, I found indeed that EE_e200z7_irq(EE_SREG level) does not pop the LIFO by writing to INTC_EOIR.R.
(The EE_e200z7_irq version for static ISR tables). In fact this version of the function does a lot less, but a critical part is therefor missing....
Or am I missing something here?
Adding
Solved the problem, but I don't know if that's enough?
Furthermore, I would also like to have ISR nesting in static interrupt table mode... Is that feature implemented? If not, I can have a go at it, to implement it, but I would need at least some assistance, and additional info on the current status.
Eagerly awaiting your replies,
Maxime Vincent
I have experimented with the EE kernel om my MPC5643L devboard, with great appreciation of the incredible work, efficiency and easy of use of the EE RTOS.
I started from a demo generated by Eclipse, using ISR_dynamic_table.
However, my application needs the least ISR jitter possible. As we are running a very time critical ISR. (just 2 time critical isrs, the rest is less time critical).
Therefor, I converted my conf.oil to use static interrupt table.
Howver, then I get following problem: The ISR fires only once, then never again. Looking at INTC_CPR, I see it is "stuck" at 7, which is the ISR priority of my interrupt that fired once. This is typical, when the priority LIFO of the INTC did not get popped.
Looking at ee_irq.c in pkg/cpu/e200zx/src, I found indeed that EE_e200z7_irq(EE_SREG level) does not pop the LIFO by writing to INTC_EOIR.R.
(The EE_e200z7_irq version for static ISR tables). In fact this version of the function does a lot less, but a critical part is therefor missing....
Or am I missing something here?
Adding
Code: Select all
/* Pop priority for external interrupts */
if (level >= EE_E200ZX_MAX_CPU_EXCP) {
/* Look at reference manual:
9.4.3.1.2 End-of-Interrupt Exception Handler NOTE
*/
EE_e200zx_mbar();
INTC_EOIR.R = 0U;
}
Furthermore, I would also like to have ISR nesting in static interrupt table mode... Is that feature implemented? If not, I can have a go at it, to implement it, but I would need at least some assistance, and additional info on the current status.
Eagerly awaiting your replies,
Maxime Vincent