Wrong spinlock implementation for Tricore?

[dcompagn]

Hi all,

I'm facing some problem using "EE_tc_sync_barrier" to synchronize the task execution.
Can that function be used inside tasks or just in the kernel?

I'd just like to be sure the spinlock mechanism, used in barriers, has been correctly implemented.
The current implementation rely on the atomicity of the CMPSWAP.W instruction, but this information is missing in the instruction set manual.
Conversely, the manual claims the atomicity for the LDMST and SWAP.W instructions.
Could someone confirm this?

Thanks in advance,
Davide

[e.guidieri]

2.4 Semaphores and Atomic Operations
The TriCore architecture has five instructions which read and/or write memory in atomic
fashion:
• LDMST (Load, Modify, Store)
• SWAP.W (Swap register with memory)
• ST.T (Store bit)
• CMPSWAP.W
• SWAPMSK.W
...

You have an old version of AURIX ISA Reference Manual, get the new one.

And I'm happy that this is the reason, because a compare and swap instrution without atomicity is meaningless.

Errico