Configuring Flash Wait Cycles on Tricore

[Alexanderv66]

On Tricore TC29x microcontrollers neccessary to configure Flash wait cycles on dependent of CPU clock speed. This is stated in the user manual.

10.5.3.3 Configuring Flash Wait Cycles
...
After System Reset and Power-On Reset the wait cycles are configured
for the clock configuration used during startup, i.e. fFSI and fFSI2 running
with maximum 100 MHz. Before changing to higher clock frequencies
this default configuration must be changed.
...

But Erika TriCore startup ee_tc_startup.c configures only that:

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/*===================== Configure CCU Clock Control =========================*/
  osEE_tc_conf_clock_ctrl();
/*===================== Configure Oscillator Control ========================*/
  osEE_tc_conf_osc_ctrl();
/*============================ Configure PLL ================================*/
  osEE_tc_set_pll_fsource(OSEE_CPU_CLOCK);

Are there any Erika built-in Flash timing configuration functions, which I can add to initialization?

[e.guidieri]

Use in .OIL

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EE_OPT="OSEE_BYPASS_CLOCK_CONFIGURATION";

to bypass the default behaviour and configure the SCU as you need at the beginning of the main before the StartOS.

Having a full driver for SCU is out of the scope of ERIKA, too complicated and I'm alone.

Errico

[Alexanderv66]

Is this definition no longer needed in OIL?

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CPU_DATA = TRICORE {
...
CPU_CLOCK = 300.0;
...
}

P.S. you alone do a great job

[e.guidieri]

Yes,

if you bypass the clock configuration declaring the CPU_CLOCK is no more needed.

In any case, System Timer driver does not trust that configuration and goes directly on the hardware to get the real frequency of the timer (since I was sure to not be able to handle all the possible configurations of the clock for any application, iI tried to make the OS independent from that).


Regards,
Errico

P.S. Thank you.

[Alexanderv66]

I have add the bypass into OIL

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OS EE {
		EE_OPT = "OSEE_DEBUG";
		EE_OPT = "OSEE_ASSERT";
		EE_OPT = "OS_EE_APPL_BUILD_DEBUG";
		EE_OPT = "OS_EE_BUILD_DEBUG";
                EE_OPT="OSEE_BYPASS_CLOCK_CONFIGURATION"; <----------
		STATUS = EXTENDED;
		ERRORHOOK = TRUE;
		USERESSCHEDULER = FALSE;
		USEORTI = TRUE;
		KERNEL_TYPE = OSEK {
			CLASS = ECC2;
			RQ = LL;
		};

And adding clock initialisation function in core0_main(). This function tested and works in a demo project without OS. And when i run this code :

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int core0_main(void)
{
	StatusType status;
	AppModeType mode;
	CoreIdType const core_id = GetCoreID();
#ifdef OSEE_BYPASS_CLOCK_CONFIGURATION
	const IfxScuCcu_PllStepsConfig IfxScuCcu_testPllConfigSteps[] = {IFXSCU_CFG_PLL_STEPS};
	IfxScuCcu_Config IfxScuCcu_testClockConfig =
	{
	    {
	        sizeof(IfxScuCcu_testPllConfigSteps) / sizeof(IfxScuCcu_PllStepsConfig),
	        (IfxScuCcu_PllStepsConfig *)IfxScuCcu_testPllConfigSteps,
	        IFXSCU_CFG_PLL_INITIAL_STEP,
	    },
	    IFXSCU_CFG_CLK_DISTRIBUTION,
	    IFXSCU_CFG_FLASH_WAITSTATE,
	    IFX_CFG_SCU_XTAL_FREQUENCY
	};
	/* standard PLL initialisation */
	IfxScuCcu_init(&IfxScuCcu_testClockConfig);
	
	//control values
	g_ScuClock.pllfreq = IfxScuCcu_getPllFrequency();
	g_ScuClock.cpufreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreIndex());
	g_ScuClock.spbfreq = IfxScuCcu_getSpbFrequency();
	g_ScuClock.gtmfreq = IfxScuCcu_getGtmFrequency();
	g_ScuClock.srifreq = IfxScuCcu_getSriFrequency();
	g_ScuClock.stmfreq = IfxScuCcu_getStmFrequency();
#endif
	if (core_id == OS_CORE_ID_MASTER)
	{
		initPeriph();
		logger = createLogger(&MODULE_ASCLIN0, 115200);
		IfxPort_setGroupState(&MODULE_P33, 6, 0xff, 0xFF);
		tellClocks();
		
		StartCore(OS_CORE_ID_1, &status);
		StartCore(OS_CORE_ID_2, &status);

		mode = OSDEFAULTAPPMODE;
	}
	else
	{

		mode = DONOTCARE;
	}

	StartOS(mode);

	return 0;
}

The code executed until line StartCore(OS_CORE_ID_2, &status); and on this line unexpectedly jumps to 0xA0000020

Снимок.JPG (18.56 KiB) Viewed 18134 times

The address 0xA0000020 has the first user instruction, as described in TC29x B-Step User’s Manual item 4.1.4 Boot Options Summary

Internal Start
In this basic startup mode, the first user instruction is fetched from address A000 0020H
in Internal Program Flash of the device.

this may indicate a processor reset.
Howewer, when i stop execution (with breakpoint) at the line StartCore(OS_CORE_ID_2, &status); and continue running ater that, then program continue normal work cycle without jumping to 0xA0000020.
I'm sure clock frequencies are correctly initialized by function IfxScuCcu_init(&IfxScuCcu_testClockConfig); because registers that modified by IfxScuCcu_init(..) are really changes value. (eg FLASH0_FCON)

Please, help me to understand what the function StartCore(OS_CORE_ID_2, &status) is waiting for.

[e.guidieri]

The fact that the code is jumping to

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int core0_main(void)

instead of main, let me suppose that you are using startup code of iLLd, and not the startup code of ERIKA, I don't know if this has an impact.

Are you sure that the data structures of the secondary cores are initialized?

The real startup id done by osEE_hal_start_core function. Try to follow the execution from there to understand what is going on, since I have no idea.

Regards,
Errico

[Alexanderv66]

I see a significant difference in the initialization of clock frequencies by means of EriKa and iLLD for TC299B. With the same frequency settings, initialization by means of Erika and initialization illd give different values of the registers sets CCUCON and PLLCON. This is acceptable and normal. But frequencies have limitations on datasheet. And these limitations are exceeded after initialization by means of Erika. For example, CPU_CLOCK = 300.0; than registers are:

• CCUCON0: 0x12220101 (SPBDIV 2, FSIDIV 2, CLKSEL 1)
• CCUCON1: 0x10001200 (STMDIV 2, GTMDIV1)
• PLLCON0: 0x01017600 (VCOBYP 0, PDIV 1, NDIV 59)
• PLLCON1: 0x00020201 (K2DIV 1, K1DIV 2)

then:

PLL output:
Fpll = Fosc*((NDIV+1)/((PDIV + 1)*(K2DIV+1))
Fpll = 20e6*(59 + 1)/((1+1)*(1+1)) = 300e6 Hz it is OK

because CLKSEL 1, then:

Fsource = Fpll = 300e6

Fspb = Fsource/SPBDIV
Fspb = 300e6/2 = 150e6 exceeded datasheet value Fspb 100 MHz max

Fsri = Fsource/SRIDIV
Fsri = 300e6/1 = 300e6 Hz it is OK

Ffsi = Fsri/FSIDIV
Ffsi = 300e6/2 = 150e6 Hz exceeded datasheet value Ffsi 100 MHz max

Fgtm = Fsource/GTMDIV
Fgtm = 300e6/1 = 300e6 exceeded datasheet value Fgtm 100 MHz max

Fstm = Fsource/STMDIV
Fstm = 300e6/2 = 150e6 exceeded datasheet value Fstm 100 MHz max

Fbaud1 = Fsource/BAUD1DIV
Fbaud1 = 300e6/1 = 300e6 exceeded datasheet value Fbaud1 100 MHz max

When i seting CPU_CLOCK = 200.0 than:

• CCUCON0: 0x12220101 (SPBDIV 2, FSIDIV 2, CLKSEL 1)
• CCUCON1: 0x10001100 (STMDIV 1, GTMDIV1)
• PLLCON0: 0x01017600 (VCOBYP 0, PDIV 1, NDIV 59)
• PLLCON1: 0x00020202 (K2DIV 2, K1DIV 2)

than:

Fpll = 20e6*(59 + 1)/((1+1)*(2+1)) = 200e6
Fsource = Fpll = 200e6
Fgtm = 200e6/1 = 200e6 exceeded datasheet value Fgtm 100 MHz max
Fstm = 200e6/1 = 200e6 exceeded datasheet value Fstm 100 MHz max

With iLLD IfxScuCcu_init() function all values not exceeded the limits

It would seem that everything is clear, use illd and everything will work. But Erika works with its own initialization and does not work with the "correct" iLLD initialization . From this I conclude that I do not correctly calculate the frequencies when the result is higher than the permissible frequencies. If you have some time for this, please correct me.

[e.guidieri]

The easiest way to understand the PLL configuration is to use the CLOCK view of Lauterbach (I see you are using it).

You can access it through a button labelled CLOCK from the view that configures MCDS (I can't be more accurate since I don't have access to lauterbach right now).

Regards,
Errico