Difference between revisions of "ARM Cortex-R"

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     MCU_DATA = TI_AWR16XX;
 
     MCU_DATA = TI_AWR16XX;
 +
 +
=== Interrupt Handling ===
 +
 +
The ERIKA3 porting on TI AWR1642 implement a VIM (Vectored Interrupt Manager) driver. The SOURCE field of ISR is mapped on ''Request'' concept of VIM.
 +
 +
The mapping between Interrupt Sources and request numbers for TI AWR1642 is done in Table of 2-11 in chapter pag 159 chapter 2 16xx/2.3 Integration 16xx/2.3.9 Vectored Interrupt Manager (MSS_VIM)/2.3.9.1 Interrupt Request Assignments of TI AWR16XX/14xx Technical Reference Manual (TI doc code swru520b)
 +
 +
'''N.B.''' Because of TI VIM hardware limitation is not possible to tie two ISR on the same priority (read Chaper 7 Vectored Interrupt Manager on TI AWR16XX/14xx TRM).
 +
 +
=== System Timer ===
 +
 +
The OSEK/VDX standard provides support for a '''System Counter''' (a counter that is automatically linked to a hardware timer).
 +
 +
In ERIKA Enterprise, this special counter has been named '''System Timer'''. To use it, you need to set a specific attribute in a Counter definition.
 +
Please note that only one counter '''for each core''' can be the System Timer.
 +
 +
A Counter which is not a System Counter must be incremented explicitly using the Autosar primitive '''IncrementCounter'''.
 +
 +
The following is an example OIL definition for a System Counter:
 +
 +
  CPU_DATA = TRICORE{
 +
    CPU_CLOCK = 200.0;
 +
    ...
 +
  };
 +
 
 +
  COUNTER SystemTimer {
 +
    CPU_ID = 0;
 +
    MINCYCLE = 1;
 +
    MAXALLOWEDVALUE = 2147483647;
 +
    TICKSPERBASE = 1;
 +
    TYPE = HARDWARE {
 +
      DEVICE = "STM_SR0";
 +
      SYSTEM_TIMER = TRUE;
 +
      PRIORITY = 1;
 +
    };
 +
    SECONDSPERTICK = 0.001;
 +
  };
 +
 +
The meaning of the various attributes is as follows:
 +
* '''CPU_DATA/CPU_CLOCK''' is used to declare the clock frequency (in MHZ).
 +
* '''COUNTER/CPU_ID''' is used to tie the counter with a specific core (if the core to be tied to is 0, explicitly declaring CPU_ID is not necessary)
 +
* '''COUNTER/TYPE''' must be set to '''HARDWARE''', and '''SYSTEM_TIMER''' must be set to true.
 +
* '''COUNTER/TYPE/DEVICE''' must be a valid device that can be used for a system timer. Currently, for TRICORE only '''STM''' (System Timer Module) MCU peripheral is a valid device for system timer. Both Interrupt source of this peripheral can be set to device and allowed values are '''STM_SR0''' and '''STM_SR1'''. '''STM_SR0''' and '''STM_SR1''' refer to the core correspindig STM comparator interrupt, so when the system timer is tied  with core0 they point to '''STM0SR0''' and '''STM0SR1''' ISRs sources respectively (Infineon naming convention).
 +
* '''COUNTER/TYPE/PRIORITY''' By default SYSTEM_TIMER is tied to smallest ISR priority (i.e. PRIORITY = 1;), but it can be overritten. Ovveride is necessay in multicore environment because priority 1 is used by the '''Intercore Interrupt Request'''.
 +
* '''COUNTER/SECONDSPERTICK''' is used to declare the wanted time duration of one hardware tick in seconds.
 +
 +
The System Timer can be attached to ALARMs as usual, as in the following example:
 +
 +
  ALARM AlarmExample {
 +
    COUNTER = SystemTimer;
 +
    ACTION  = ACTIVATETASK{
 +
      TASK = TaskExample;
 +
    };
 +
  };
 +
  
 
[[Category:Architectures]]
 
[[Category:Architectures]]

Revision as of 19:59, 25 February 2019

ERIKA Enterprise supports the ARM Cortex-R architecture. The support has been succesfully tested on Texas Instruments AWR1642.

We also have an internal porting of the RTOS for the Cortex-R5 on Xilinx Ultrascale+. Such support will be released in the next months. Please, contact us in case of urgent need.

Introduction

This manual describes the porting details of the ERIKA Enterprise v3 kernel(s) for families of microcontrollers which integrate ARM Cortex-R CPUs.

Configuration and Programming

ERIKA Enterprise is configured through RT-Druid and an OIL file and some other properties. The description of special fields and property have been separated by MCU.

Cortex-R MCU supported

All the Cortex-R microcontroller will need the CPU_DATA configured as Cortex-R as follow

CPU

CPU_DATA object must be set to CORTEX_R.

Example of a CPU_DATA section: 

   CPU_DATA = CORTEX_R {
     ...
   };

Support for TI AWR16XX

The following sections describe the properties and OIL fields customized for TI AWR 1642 ARM Cortex-R architecture.

The support for TI AWR16XX have been developed on

Evaluation Board:

Using TI ARM CGT compiler:

As debugger we used XDS110-based JTAG on the through the Code Composer Studio IDE

Having the MMWave DEVPACK it is possible to use lauterbach TRACE32 too

The porting integrates with TI mmWave SDK library. mmWave SDK is a requisite for the porting.

The version integrated is the latest LTS at the moment of the porting

Tutorial

The following tutorials are available for this architecture:

TI ARM CGT Compiler Path

It is possible to choose the path in three different ways:

  • Specific environment variables: TI_ARM_C_DIR
    • E.g.: TI_ARM_C_DIR=C:\ti\ccsv8\tools\compiler\ti-cgt-arm_18.1.4.LTS
  • RT-Druid Eclipse IDE Property.
  • RT-Druid Configuration File Entry: preference_cortex_r__path_for_ti_cgt_arm_compiler
    • E.g.: preference_cortex_r__path_for_ti_cgt_arm_compiler=C:\ti\ti-cgt-arm_16.9.6.LTS

N.B. mmWave SDK 02_01_00_04 came with ti-cgt-arm_16.9.6.LTS packet

mmWave SDK Path

As we already this is a strict dependency for this porting so the following must be provided

It is possible to choose the path in three different ways:

  • Specific environment variables: TI_MMWAVE_SDK_PATH
    • E.g.: TI_MMWAVE_SDK_PATH=C:\\ti\\mmwave_sdk_02_01_00_04
  • RT-Druid Eclipse IDE Property.
  • RT-Druid Configuration File Entry: preference_cortex_r__path_for_ti_mmwave_sdk
    • E.g.: preference_cortex_r__path_for_ti_mmwave_sdk=C:\\ti\\mmwave_sdk_02_01_00_04

Here is an example of RT-Druid configuration file.

Porting for TI AWR1642 supporte the following under attributes for CPU_DATA CORTEX_R

COMPILER

COMPILER attribute of CPU_DATA must be set to TI_CGT_ARM.

Example of a COMPILER attribute of CPU_DATA section: 

   CPU_DATA = CORTEX_R {
     COMPILER = TI_CGT_ARM;
     ...
   };

MINIMAL_OPTS

MINIMAL_OPTS boolean property of COMPILER attribute of CPU_DATA configures the build system with minimal compiling and linking options. The default value is set to FALSE.

Example of a MINIMAL_OPTS property of COMPILER attribute of CPU_DATA section: 

   CPU_DATA = CORTEX_R {
     COMPILER = TI_CGT_ARM{
          MINIMAL_OPTS = TRUE;
     };
     ...
   };

MCU_DATA

MCU_DATA must be set to TI_AWR16XX.

Example of MODEL attribute of a MCU_DATA section: 

   MCU_DATA = TI_AWR16XX;

Interrupt Handling

The ERIKA3 porting on TI AWR1642 implement a VIM (Vectored Interrupt Manager) driver. The SOURCE field of ISR is mapped on Request concept of VIM.

The mapping between Interrupt Sources and request numbers for TI AWR1642 is done in Table of 2-11 in chapter pag 159 chapter 2 16xx/2.3 Integration 16xx/2.3.9 Vectored Interrupt Manager (MSS_VIM)/2.3.9.1 Interrupt Request Assignments of TI AWR16XX/14xx Technical Reference Manual (TI doc code swru520b)

N.B. Because of TI VIM hardware limitation is not possible to tie two ISR on the same priority (read Chaper 7 Vectored Interrupt Manager on TI AWR16XX/14xx TRM).

System Timer

The OSEK/VDX standard provides support for a System Counter (a counter that is automatically linked to a hardware timer).

In ERIKA Enterprise, this special counter has been named System Timer. To use it, you need to set a specific attribute in a Counter definition. Please note that only one counter for each core can be the System Timer.

A Counter which is not a System Counter must be incremented explicitly using the Autosar primitive IncrementCounter.

The following is an example OIL definition for a System Counter: 

 CPU_DATA = TRICORE{
   CPU_CLOCK = 200.0;
   ...
 };
 
 COUNTER SystemTimer {
   CPU_ID = 0;
   MINCYCLE = 1;
   MAXALLOWEDVALUE = 2147483647;
   TICKSPERBASE = 1;
   TYPE = HARDWARE {
     DEVICE = "STM_SR0";
     SYSTEM_TIMER = TRUE;
     PRIORITY = 1;
   };
   SECONDSPERTICK = 0.001;
 };

The meaning of the various attributes is as follows:

  • CPU_DATA/CPU_CLOCK is used to declare the clock frequency (in MHZ).
  • COUNTER/CPU_ID is used to tie the counter with a specific core (if the core to be tied to is 0, explicitly declaring CPU_ID is not necessary)
  • COUNTER/TYPE must be set to HARDWARE, and SYSTEM_TIMER must be set to true.
  • COUNTER/TYPE/DEVICE must be a valid device that can be used for a system timer. Currently, for TRICORE only STM (System Timer Module) MCU peripheral is a valid device for system timer. Both Interrupt source of this peripheral can be set to device and allowed values are STM_SR0 and STM_SR1. STM_SR0 and STM_SR1 refer to the core correspindig STM comparator interrupt, so when the system timer is tied with core0 they point to STM0SR0 and STM0SR1 ISRs sources respectively (Infineon naming convention).
  • COUNTER/TYPE/PRIORITY By default SYSTEM_TIMER is tied to smallest ISR priority (i.e. PRIORITY = 1;), but it can be overritten. Ovveride is necessay in multicore environment because priority 1 is used by the Intercore Interrupt Request.
  • COUNTER/SECONDSPERTICK is used to declare the wanted time duration of one hardware tick in seconds.

The System Timer can be attached to ALARMs as usual, as in the following example: 

 ALARM AlarmExample {
   COUNTER = SystemTimer;
   ACTION  = ACTIVATETASK{
      TASK = TaskExample;
   };
 };
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