ARM Cortex-M

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Introduction

This manual describes the porting details of the ERIKA Enterprise v3 kernel(s) for families of microcontrollers which integrate ARM Cortex-M CPUs.

Cortex-M features supported

The following are the main features of the currently implemented support:

Additionally, we are porting ERIKA3 also on a ARM Cortex-M7 CPU on ST 32F746GDISCOVERY board with STM32F746NG MCU.

In the next months, the public code will be delivered through the GitHub repository. In case of urgent need, please contact us.

Tutorials

The following tutorials are available for this architecture:

Configuration and Programming

ERIKA Enterprise is configured through RT-Druid and an OIL file and some other properties.

The following sections describe the properties and OIL fields customized for ARM Cortex-M architecture.

GCC Compiler Path

It is possible to choose the path in three different ways:

  • Specific environment variables: ARM_TOOLS
    • E.g.: ARM_TOOLS=C:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q3
  • RT-Druid Eclipse IDE Property.
  • RT-Druid Configuration File Entry: preference_cortex_m__path_for_gcc_compiler
    • E.g.: preference_cortex_m__path_for_gcc_compiler=C:\Program Files (x86)\GNU Tools ARM Embedded\4.9 2015q3

Here is an example of RT-Druid configuration file.

S32 SDK Path

It is possible to choose the path in three different ways:

  • Specific environment variables: S32_SDK_FILES
    • E.g.: S32_SDK_FILES=C:\NXP\S32DS_ARM_v2.0\S32DS\S32SDK_S32K14x_EAR_0.8.4
  • RT-Druid Eclipse IDE Property.
  • RT-Druid Configuration File Entry: preference_cortex_m__path_for_s32_sdk
    • E.g.: preference_cortex_m__path_for_s32_sdk=C:\NXP\S32DS_ARM_v2.0\S32DS\S32SDK_S32K14x_EAR_0.8.4

Here is an example of RT-Druid configuration file.

Lauterbach TRACE32 Path

It is possible to choose the path in two different ways:

  • RT-Druid Eclipse IDE Property.
  • RT-Druid Configuration File Entry: preference_lauterbach__path_for_trace32
    • E.g.: preference_lauterbach__path_for_trace32=C:\T32

Here is an example of RT-Druid configuration file.

Lauterbach Emulator Interface

It is possible to choose the path in two different ways:

  • RT-Druid Eclipse IDE Property.
  • RT-Druid Configuration File Entry: preference_lauterbach__emulator_usb_interface
    • E.g.: preference_lauterbach__emulator_usb_interface=true

Here is an example of RT-Druid configuration file.

CPU

CPU_DATA object must be set to CORTEX_M.

Example of a CPU_DATA section:

   CPU_DATA = CORTEX_M {
     ...
   };

MODEL

MODEL attribute of CPU_DATA supports for now the M4 and M4F values only. Deafult value is M4.

Example of a MODEL attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     ...
   };

FPU Support

Selecting M4F in the MODEL attribute of CPU_DATA the FPU support is enabled by default.

To disable the FPU support the DISABLE_FPU sub-field of M4F model SHALL be se to TRUE as shown in the following example:

   CPU_DATA = CORTEX_M {
     MODEL = M4F {
          DISABLE_FPU = TRUE;
     };
     ...
   };

COMPILER

COMPILER attribute of CPU_DATA supports for now the GCC value only. Deafult value is GCC.

Example of a COMPILER attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     COMPILER = GCC;
     ...
   };

MINIMAL_OPTS

MINIMAL_OPTS boolean property of COMPILER attribute of CPU_DATA configures the build system with minimal compiling and linking options. The default value is set to FALSE.

Example of a MINIMAL_OPTS property of COMPILER attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     COMPILER = GCC {
          MINIMAL_OPTS = TRUE;
     };
     ...
   };

EXECUTE_FROM_RAM

EXECUTE_FROM_RAM attribute of CPU_DATA configures the build system generate binary to execute the application in RAM. The default value is set to FALSE.

Example of a COMPILER attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     EXECUTE_FROM_RAM = TRUE;
     ...
   };

TRACER

TRACER attribute of CPU_DATA configures the build system to generate Lauterbach TRACE32 scripts to enable the tracing support. This attribute make sense in the MCUs that implements ITM and/or ETM hardware. Supported values are OFF, SWO and OFFCHIP. The default value is set to OFF.

Example of a TRACER attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     TRACER = OFFCHIP;
     ...
   };

SYS_STACK_SIZE

SYS_STACK_SIZE attribute of CPU_DATA configures the size in bytes of the system stack. The default value is set to 1024.

Example of a TRACER attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     SYS_STACK_SIZE = 2048;
     ...
   };

MCU

MCU_DATA object supports for now the S32K1XX value only.

Example of a MCU_DATA section:

   MCU_DATA = S32K1XX {
     ...
   };

MODEL

MODEL attribute of MCU_DATA supports for now the S32K144 and S32K148 values only. Default value is S32K144.

Example of MODEL attribute of a MCU_DATA section:

   MCU_DATA = S32K1XX {
     MODEL = S32K148;
     ...
   };

BOARD

BOARD_DATA object supports for now the S32K144EVB_Q100 and S32K148EVB_Q144_Q176 values only. Default value is NO_BOARD.

Example of a BOARD_DATA section:

 BOARD_DATA = S32K148EVB_Q144_Q176;

LIB

LIB object supports for now the S32_SDK value only.

Example of a LIB section:

   LIB = S32_SDK {
     ...
   };

S32 SDK

The following sections describe the OIL fields of the LIB object customized for the official S32 SDK supports.

BOARD

BOARD attribute of S32_SDK supports for now S32K144EVB_Q100 and S32K148EVB_Q144_Q176 values only. Default value is S32K144EVB_Q100.

Example of SDK_BOARD attribute of ARDUINO:

   LIB = S32_SDK {
     BOARD = S32K148EVB_Q144_Q176;
     ...
   };

VERSION

VERSION attribute of S32_SDK supports for now the "0.8.4 EAR" value only.

Example of VERSION attribute of S32_SDK:

   LIB = S32_SDK {
     BOARD = S32K148EVB_Q144_Q176;
     VERSION = "0.8.4 EAR";
     ...
   };

STAND_ALONE

STAND_ALONE boolean attribute of S32_SDK configures the build system to generate or not libs32sdk.a stand-alone binary library. The default value is set to TRUE. Default value is TRUE.

Example of STAND_ALONE attribute of S32_SDK:

   LIB = S32_SDK {
     BOARD = S32K148EVB_Q144_Q176;
     VERSION = "0.8.4 EAR";
     STAND_ALONE = TRUE;
   };

Interrupt Handling

The Interrupt Handling support is microcontroller dependent. For each supported microcontroller family, the ISRs configuration of ERIKA3 is shown below.

S32K1XX Family

The S32K1XX family microcontrollers has an interrupt vector table which is stored in the flash memory. The complete list of SOURCE entries is shown below.

  • Traps
    • NMI: Non-maskable Interrupt (NMI) Trap
    • HARD_FAULT: Hard Fault Trap
    • BUS_FAULT: Bus Fault Trap
    • USAGE_FAULT: Usage Fault Trap
    • DEBUG_MONITOR: Debug Monitor Trap
    • SYSTICK: SysTick Trap
  • Interrupts
    • DMA0: DMA channel 0 transfer complete
    • DMA1: DMA channel 1 transfer complete
    • DMA2: DMA channel 2 transfer complete
    • DMA3: DMA channel 3 transfer complete
    • DMA4: DMA channel 4 transfer complete
    • DMA5: DMA channel 5 transfer complete
    • DMA6: DMA channel 6 transfer complete
    • DMA7: DMA channel 7 transfer complete
    • DMA8: DMA channel 8 transfer complete
    • DMA9: DMA channel 9 transfer complete
    • DMA10: DMA channel 10 transfer complete
    • DMA11: DMA channel 11 transfer complete
    • DMA12: DMA channel 12 transfer complete
    • DMA13: DMA channel 13 transfer complete
    • DMA14: DMA channel 14 transfer complete
    • DMA15: DMA channel 15 transfer complete
    • DMA_ERR: DMA error interrupt channels 0-15
    • MCM_FPU: FPU sources
    • FTFC_CMD: FTFC Command complete
    • FTFC_RDC: FTFC Read collision
    • PMC_LVD: PMC Low voltage detect interrupt
    • FTFC_FAULT: FTFC Double bit fault detect
    • WDOG_EVM: Single interrupt vector for WDOG and EWM
    • RCM: RCM Asynchronous Interrupt
    • LPI2C0_MASTER:LPI2C0 Master Interrupt
    • LPI2C0_SLAVE: LPI2C0 Slave Interrupt
    • LPSPI0: LPSPI0 Interrupt
    • LPSPI1: LPSPI1 Interrupt
    • LPSPI2: LPSPI2 Interrupt
    • LPI2C1_MASTER:LPI2C1 Master Interrup
    • LPI2C1_SLAVE: LPI2C1 Slave Interrupt
    • LPUART0: LPUART0 Transmit
    • LPUART1: LPUART1 Transmit
    • LPUART2: LPUART2 Transmit
    • ADC0: ADC0 interrupt request
    • ADC1: ADC1 interrupt request
    • CMP0: CMP0 interrupt request
    • ERM_SINGLE: ERM single bit error correction
    • ERM_DOUBLE: ERM double bit error non-correctable
    • RTC_ALARM: RTC alarm interrupt
    • RTC_SECONDS: RTC seconds interrupt
    • LPIT0_CH0: LPIT0 channel 0 overflow interrupt
    • LPIT0_CH1: LPIT0 channel 1 overflow interrupt
    • LPIT0_CH2: LPIT0 channel 2 overflow interrupt
    • LPIT0_CH3: LPIT0 channel 3 overflow interrupt
    • PDB0: PDB0 interrupt
    • SAI1_TX: SAI1 Transmit Synchronous interrupt
    • SAI1_RX: SAI1 Receive Synchronous interrupt
    • SCG: SCG bus interrupt request
    • LPTMR0: LPTIMER0 interrupt request
    • PORTA: Port A pin detect interrupt
    • PORTB: Port B pin detect interrupt
    • PORTC: Port C pin detect interrupt
    • PORTD: Port D pin detect interrupt
    • PORTE: Port E pin detect interrupt
    • SWI: Software interrupt
    • QSPI0: QSPI All interrupts ORed output
    • PDB1: PDB1 interrupt
    • FLEXIO: FlexIO Interrupt
    • SAI0_TX: SAI0 Transmit Synchronous interrupt
    • SAI0_RX: SAI0 Receive Synchronous interrupt
    • ENET_TIMER: ENET 1588 Timer Interrupt - synchronous
    • ENET_TX: ENET Data transfer done
    • ENET_RX: ENET Receive Buffer Done for Ring/Queue 0
    • ENET_ERR: ENET Payload receive error
    • ENET_STOP: ENET Graceful stop
    • ENET_WAKE: ENET Wake from sleep
    • CAN0_ORED: CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]
    • CAN0_ERR: CAN0 Interrupt indicating that errors were detected on the CAN bus
    • CAN0_WAKE: CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode
    • CAN0_ORED_0_15: CAN0 OR'ed Message buffer (0-15)
    • CAN0_ORED_16_31: CAN0 OR'ed Message buffer (16-31)
    • CAN1_ORED: CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]
    • CAN1_ERR: CAN1 Interrupt indicating that errors were detected on the CAN bus
    • CAN1_ORED_0_15: CAN1 OR'ed Message buffer (0-15)
    • CAN1_ORED_16_31: CAN0 OR'ed Message buffer (16-31)
    • CAN2_ORED: CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]
    • CAN2_ERR: CAN0 Interrupt indicating that errors were detected on the CAN bus
    • CAN2_ORED_0_15: CAN1 OR'ed Message buffer (0-15)
    • CAN2_ORED_16_31: CAN0 OR'ed Message buffer (16-31)
    • FTM0_CH0_CH1: FTM0 Channel 0 and 1 interrupt
    • FTM0_CH2_CH3: FTM0 Channel 2 and 3 interrupt
    • FTM0_CH4_CH5: FTM0 Channel 4 and 5 interrupt
    • FTM0_CH6_CH7: FTM0 Channel 6 and 7 interrupt
    • FTM0_FAULT: FTM0 Fault interrupt
    • FTM0_OVF_RELOAD: FTM0 Counter overflow and Reload interrupt
    • FTM1_CH0_CH1: FTM1 Channel 0 and 1 interrupt
    • FTM1_CH2_CH3: FTM1 Channel 2 and 3 interrupt
    • FTM1_CH4_CH5: FTM1 Channel 4 and 5 interrupt
    • FTM1_CH6_CH7: FTM1 Channel 6 and 7 interrupt
    • FTM1_FAULT: FTM1 Fault interrupt
    • FTM1_OVF_RELOAD: FTM1 Counter overflow and Reload interrupt
    • FTM2_CH0_CH1: FTM2 Channel 0 and 1 interrupt
    • FTM2_CH2_CH3: FTM2 Channel 2 and 3 interrupt
    • FTM2_CH4_CH5: FTM2 Channel 4 and 5 interrupt
    • FTM2_CH6_CH7: FTM2 Channel 6 and 7 interrupt
    • FTM2_FAULT: FTM2 Fault interrupt
    • FTM2_OVF_RELOAD: FTM2 Counter overflow and Reload interrupt
    • FTM3_CH0_CH1: FTM3 Channel 0 and 1 interrupt
    • FTM3_CH2_CH3: FTM3 Channel 2 and 3 interrupt
    • FTM3_CH4_CH5: FTM3 Channel 4 and 5 interrupt
    • FTM3_CH6_CH7: FTM3 Channel 6 and 7 interrupt
    • FTM3_FAULT: FTM3 Fault interrupt
    • FTM3_OVF_RELOAD: FTM3 Counter overflow and Reload interrupt
    • FTM4_CH0_CH1: FTM4 Channel 0 and 1 interrupt
    • FTM4_CH2_CH3: FTM4 Channel 2 and 3 interrupt
    • FTM4_CH4_CH5: FTM4 Channel 4 and 5 interrupt
    • FTM4_CH6_CH7: FTM4 Channel 6 and 7 interrupt
    • FTM4_FAULT: FTM4 Fault interrupt
    • FTM4_OVF_RELOAD: FTM4 Counter overflow and Reload interrupt
    • FTM5_CH0_CH1: FTM5 Channel 0 and 1 interrupt
    • FTM5_CH2_CH3: FTM5 Channel 2 and 3 interrupt
    • FTM5_CH4_CH5: FTM5 Channel 4 and 5 interrupt
    • FTM5_CH6_CH7: FTM5 Channel 6 and 7 interrupt
    • FTM5_FAULT: FTM5 Fault interrupt
    • FTM5_OVF_RELOAD: FTM5 Counter overflow and Reload interrupt
    • FTM6_CH0_CH1: FTM6 Channel 0 and 1 interrupt
    • FTM6_CH2_CH3: FTM6 Channel 2 and 3 interrupt
    • FTM6_CH4_CH5: FTM6 Channel 4 and 5 interrupt
    • FTM6_CH6_CH7: FTM6 Channel 6 and 7 interrupt
    • FTM6_FAULT: FTM6 Fault interrupt
    • FTM6_OVF_RELOAD: FTM6 Counter overflow and Reload interrupt
    • FTM7_CH0_CH1: FTM7 Channel 0 and 1 interrupt
    • FTM7_CH2_CH3: FTM7 Channel 2 and 3 interrupt
    • FTM7_CH4_CH5: FTM7 Channel 4 and 5 interrupt
    • FTM7_CH6_CH7: FTM7 Channel 6 and 7 interrupt
    • FTM7_FAULT: FTM7 Fault interrupt
    • FTM7_OVF_RELOAD: FTM7 Counter overflow and Reload interrupt

OSEK/VDX Extensions

This Section contains information about the OSEK/VDX Extensions (or optional features) that have been implemented for the Arm Cortex-M support.

System Timer

System Timer counter is implemented using SysTick of Cortex-M CPUso the DEVICE attribute MUST be se to SYSTICK as shown below.

Example of a System Timer counter:

   COUNTER SystemTimer {
     MINCYCLE = 1;
     MAXALLOWEDVALUE = 65535;
     TICKSPERBASE = 1;
     TYPE = HARDWARE {
       DEVICE = "SYSTICK";
       SYSTEM_TIMER = TRUE;
     };
     SECONDSPERTICK = 0.001;
   };

CPU_CLOCK

System Timer need the CPU_CLOCK attribute of CPU_DATA. This value, expressed as MHz, must be set to the configured frequency of the CPU.

Example of a CPU_CLOCK attribute of CPU_DATA section:

   CPU_DATA = CORTEX_M {
     MODEL = M4;
     CPU_CLOCK = 48.0;
     ...
   };