Issue with Interrupt Vector Table (TriCore)

[AlTi]

Hi,

I have found an issue with the Interrupt Vector Table, which can lead to wrong entry address calculations, because the TriCore needs the Interrupt Vector Table to be aligned to addresses where Bits [12:5] are 0. In the TriCore´s architecture manual (vol1) you can find a more detailed discription (look out for figure 5-2).
I solved this problem in my application by aligning the interrupt table vector to 0x1000 with the linker script template "ee_tc2Yx_gnu_relocable.ld.tmpl".

Code: Select all

  /*
   * Section for interrupt table
   */
  CORE_SEC(.inttab) 0 : ALIGN(0x1000)
  {
    *(.inttab)
    *(.*.inttab)
  }

I hope, this helps.

[paolo.gai]

Thanks for your post!

We'll sure take a look at it soon and patch the linker script. The issue never came up during our development, we'll also investigate why.

Ciao,

PJ

[e.guidieri]

The linker files to be patched are ee/pkg/mcu/infineon_common_tc2Y/{ee_tc2Yx_gnu_flash.ld.tmpl,ee_tc2Yx_global_gnu_ram.ld}

The one you used works on object code level (probably adding alignment requirement object sections), not at relocation level, and only if activate the Single ELF Build.

And for, for what I understood, to be sure that you could use Bit[12] (used by priorities greater than 127) you should ALIGN at 0x2000 (8192).

Ciao,
Errico

[AlTi]

Yes, you are right with the alignment. It should be at 0x2000.

Thank you,
Alex